LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY decoder3_8 IS
PORT (i:in std_logic_vector(2 downto 0);
		y:out std_logic_vector(7 downto 0));
END decoder3_8;

ARCHITECTURE func OF decoder3_8 IS
begin
		process(i)
		begin
		y<="11111111";
		case i is
		when "000"=>y(0)<='0';
		when "001"=>y(1)<='0';
		when "010"=>y(2)<='0';
		when "011"=>y(3)<='0';
		when "100"=>y(4)<='0';
		when "101"=>y(5)<='0';
		when "110"=>y(6)<='0';
		when "111"=>y(7)<='0';
		when others=>y<="11111111";
		end case;
		end process;
end architecture;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY nand_2 IS
PORT (a,b,c,d:in std_logic;
		out_y:out std_logic);
end nand_2;

architecture Dataflow of nand_2 IS
begin
out_y<=(not a or not b or not c or not d);
end Dataflow;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY fulladder IS
PORT (a,b,ci:IN STD_LOGIC;
		s,co:OUT STD_LOGIC);
END fulladder;

ARCHITECTURE Structural OF fulladder IS
COMPONENT decoder3_8
PORT(i:in std_logic_vector(2 downto 0);
		y:out std_logic_vector(7 downto 0));
END COMPONENT;

COMPONENT nand_2
PORT (a,b,c,d:in std_logic;
		out_y:out std_logic);
END COMPONENT;
SIGNAL zl,xl,cl,vl,bl,nl,ml:STD_LOGIC;

BEGIN
	U1:decoder3_8 PORT MAP (i(0)=>a,i(1)=>b,i(2)=>ci,
						y(1)=>zl,y(2)=>xl,y(4)=>cl,y(7)=>vl,y(3)=>bl,y(5)=>nl,y(6)=>ml);
	U2:nand_2 PORT MAP(a=>zl,b=>xl,c=>cl,d=>vl,
					out_y=>s);
	U3:nand_2 PORT MAP(a=>bl,b=>nl,c=>ml,d=>vl,
					out_y=>co);
END Structural;